1. Field
The present disclosure relates to systems and techniques for identifying process and temperature of chips.
2. Background
The demand for wireless services has led to the development of an ever increasing number of chips, all of which must adhere to strict industry performance standards. Manufacturing of silicon chips is guided in part by standards and tolerances for nominal process speed. Within the guidelines of such standards, chips are designed to run at their rated clock speed for their entire expected lifetime, even in worst-case temperature and voltage conditions. Thus, part of the manufacturing process includes testing manufactured chips to identify their rated clock speed and ensure they are rated properly.
Chips for use in communications devices must generally be rated to operate at a specified nominal speed, within a certain allowed tolerance. However, a set of chips generated from a single wafer commonly will fall into a range of different process speed ratings.
In an attempt to use those portions of the wafer that produce different speed ratings, some manufacturers engage in a method of speed binning, in which the various chips produced from a single wafer are tested and batched according to their graded process speed. Batching chips according to their speed may be time consuming and costly.
Some manufacturers may even discard slow chips and fast chips that are outside of the nominal tolerance range. For example, SDRAM chips require an external clock from the host controller with control and data signals. Because the host clock is sensitive to process speed, temperature and voltage variations, it is possible that a given set of parameters used to generate timing in a controller may not hold true across all process speed, temperature and voltage variations. In such cases speed binning is commonly used. This involves sorting chips according to different speed settings, and even providing software customized for different speeds. Of course, such customized operations can be very costly.
There have been attempts to compensate for effects of a chip's operating temperature on its clock speed, however such methods have proven cumbersome. For example, additional components for measuring chip temperature and providing leads to communicate such temperature to compensation circuitry have been employed in the past. However, the additional components and leads consume valuable space on the silicon chip, and require additional costly manufacturing steps and parts.
Accordingly, there is a need for a methodology wherein all chips from a single wafer are enabled to operate at an industry specification nominal speed, regardless of temperature variations that occur during the wafer fabrication, and regardless of temperature variations that may occur during use. The specific methodology should provide an ability to determine operating temperature and process speed while a chip is in use, without implementing additional chip components or new manufacturing steps.